Silicon wafers are produced as precursors from which microelectronic semiconductor components are produced. The wafers are cleaved from cylindrical silicon crystals, parallel to their major surfaces, to produce thin disks, typically 20-30 cm in diameter. The resulting wafers must be polished to give flat and planar surfaces for proper formation of electronic components to form integrated chip semiconductor devices. Typically, a 20-cm diameter wafer will produce 100 or more microprocessor chips.
The designed size of such integrated chips is steadily decreasing, while the number of layers applied, e.g. by various sequences of depositing, patterning, and etching of features onto the silicon surface, is rising. Present semiconductors typically incorporate up to 7 or 8 metal layers, and it is expected that future designs will contain even more layers. The decrease in the size of circuitry and the increase in the number of layers applied are leading to ever more stringent requirements on the smoothness and planarity of the silicon and semiconductor wafers throughout the chip manufacturing process, since uneven surfaces may undermine the patterning process and the general integrity of the resulting circuit.
The standard wafer polishing technique in use at present is to position a wafer over a rotating polishing pad that is usually disk shaped, and is mounted on a large turntable. A chemical-mechanical polishing (CMP) slurry is usually applied to the surface of the pad, and the wafer is held in place by an overhead wafer carrier whilst being polished by the rotating pad and slurry. This is an adaptation of optical polishing technology used for polishing lenses, mirrors, and other optical components.
A significantly different approach is so-called Linear Planarization Technology (LPT), wherein the polishing pad is mounted onto a supporting belt. One such pad and belt combination, described in EP-A-0696495, comprises a conventional flat polyurethane polishing pad glued to a lower belt of sheet steel or other high strength material.
A disadvantage of such prior art polishing pads is that they often contain seams. A polishing pad is often subject to delamination at its seams. Moreover, the seams can mar the surface of a polished article, and can limit the ability of a pad to polish the article to a high degree of planarity. A large pad made from two or more smaller pads will have one or more seams at the junctions of the smaller pads. See, e.g., U.S. Pat. No. 6,179,950 (Zhang et al). Also, whenever the ends of an elongated pad are joined to create a belt, the belt contains a seam at the junction. See, e.g., WO 01/83167 (Eppert et al.)
One way to solve the seam problem is to directly create the polishing layer in the size and shape desired. That may be accomplished by, e.g., casting a continuous, seamless polishing layer having the desired dimensions. See, e.g., WO 99/06182 (Dudovicz et al).
Wafer polishing using either the rotating disk or endless belt techniques typically involves stacking a hard polishing layer onto a rigid support. For example, the platen beneath a rotating polishing disk typically comprises steel, and an endless polishing belt typically comprises a stainless steel supporting belt. For that reason, it is often desirable to incorporate into the polishing pad a relatively soft, compressible subpad below the polishing layer. See, e.g., U.S. Pat. No. 5,403,228 (Pasch). In use, the compressible subpad is sandwiched between the polishing layer and the steel platen or belt support, which allows the hard polishing layer to better conform to the surface of the wafer.
According to prior art construction methods, where seams can be a problem, a polishing layer is attached to a compressible subpad using, e.g., double sided tape, and the stacked pad is attached to the steel platen or stainless steel belt in the same manner. We have found that when a seamless polishing layer is created directly over a compressible subpad by coating it with a hardenable fluid, the hardenable fluid generally penetrates into the porous subpad. This causes air to be displaced from the subpad into the hardenable fluid, which can create voids in the hardened polishing layer. Moreover, the fluid often penetrates to different depths at different locations throughout the subpad, and from subpad to subpad. Consequently, the hardened polishing layer created in these pads varies in thickness, as does the thickness of the unpenetrated portion of the subpad below the hardened polishing layer. The polishing layer voids and the variability in the thickness of the hardened polishing layer and of the subpad material thereunder cause a corresponding variability in the compressibility of the polishing pad. As discussed earlier in connection with the seam problem, when the properties of the polishing pad are not uniform, it can limit the pad's ability to impart uniform levels of smoothness and planarity to a polished item, whether it be a silicon wafer, an optical component, or another article.
Consequently, a need exists for a polishing pad including a seamless polishing layer having a substantially uniform depth of penetration into a porous subpad, and for a method of making the seamless, porous subpad-containing polishing pad from a hardenable fluid.